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FPL
2009
Springer
101views Hardware» more  FPL 2009»
14 years 4 months ago
An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
Tobias Schumacher, Christian Plessl, Marco Platzne...
FPL
2009
Springer
120views Hardware» more  FPL 2009»
14 years 4 months ago
Using 3D integration technology to realize multi-context FPGAs
This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a...
Alessandro Cevrero, Panagiotis Athanasopoulos, Had...
FPL
2009
Springer
113views Hardware» more  FPL 2009»
14 years 4 months ago
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
Brian Van Essen, Aaron Wood, Allan Carroll, Stephe...
FPL
2009
Springer
117views Hardware» more  FPL 2009»
14 years 4 months ago
CNP: An FPGA-based processor for Convolutional Networks
Clément Farabet, Cyril Poulet, Jefferson Y....
FPL
2009
Springer
63views Hardware» more  FPL 2009»
14 years 4 months ago
Towards a unique FPGA-based identification circuit using process variations
Haile Yu, Philip H. W. Leong, Heiko Hinkelmann, Le...
FPL
2009
Springer
148views Hardware» more  FPL 2009»
14 years 4 months ago
Comparing fine-grained performance on the Ambric MPPA against an FPGA
A simple image-processing application is implemented on the Ambric MPPA and an FPGA, using a similar implementation for both devices. FPGAs perform extremely well on this kind of ...
Brad L. Hutchings, Brent E. Nelson, Stephen West, ...
FPL
2009
Springer
96views Hardware» more  FPL 2009»
14 years 4 months ago
Noise impact of single-event upsets on an FPGA-based digital filter
Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets ...
Brian H. Pratt, Michael J. Wirthlin, Michael P. Ca...
FPL
2009
Springer
145views Hardware» more  FPL 2009»
14 years 4 months ago
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...
FPL
2009
Springer
130views Hardware» more  FPL 2009»
14 years 4 months ago
Tracking elephant flows in internet backbone traffic with an FPGA-based cache
This paper presents an FPGA-friendly approach to tracking elephant flows in network traffic. Our approach, Single Step Segmented Least Recently Used (S3 -LRU) policy, is a netwo...
Martin Zádník, Marco Canini, Andrew ...
FPL
2009
Springer
107views Hardware» more  FPL 2009»
14 years 4 months ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...