FPT
2005
IEEE
14 years 5 months ago
2005
IEEE
This paper describes a class of FPGA-specific uniform random number generators with a 2k −1 length period, which can provide k random bits per-cycle for the cost of k Lookup Ta...
FPT
2005
IEEE
14 years 5 months ago
2005
IEEE
FPT
2005
IEEE
14 years 5 months ago
2005
IEEE
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
FPT
2005
IEEE
14 years 5 months ago
2005
IEEE
Producing a functionally correct integrated circuit is becoming increasingly difficult. No matter how careful a designer is, there will always be integrated circuits that are fabr...
FPT
2005
IEEE
14 years 5 months ago
2005
IEEE
Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipeli...
FPT
2005
IEEE
14 years 5 months ago
2005
IEEE
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework compr...
FPT
2005
IEEE
14 years 5 months ago
2005
IEEE
Two FPGA implementations of a Shape Adaptive Discrete Cosine Transform (SA-DCT) accelerator are presented in this paper: one PCI-based and the other AMBA-based. The former is used...
FPT
2005
IEEE
14 years 5 months ago
2005
IEEE
This paper describes the design and implementation of hardware architectures for posture analysis. Posture analysis is an active research area in computer vision. It can be used i...
FPT
2005
IEEE
14 years 5 months ago
2005
IEEE
FPT
2005
IEEE
14 years 5 months ago
2005
IEEE
The performance of security applications can be greatly improved by accelerating the cryptographic algorithms in hardware. In this paper, an implementation of the Secure Shell (SS...