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DATE
1999
IEEE
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DATE 1999
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FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
14 years 3 months ago
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www.cecs.uci.edu
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
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