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34
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ISPD
2003
ACM
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ISPD 2003
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Explicit gate delay model for timing evaluation
14 years 4 months ago
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www.cecs.uci.edu
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
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