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    GLVLSI
    1998
    IEEE
    130views VLSI» more  GLVLSI 1998»
    Design Issues of LC Tuned Oscillators for Integrated Transceivers
    13 years 11 months ago
    Design Issues of LC Tuned Oscillators for Integrated Transceivers
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    Carlo Samori, Andrea L. Lacaita, Alfio Zanchi, P. ...
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    GLVLSI
    1998
    IEEE
    101views VLSI» more  GLVLSI 1998»
    A New Full Adder Cell for Low-Power Applications
    13 years 11 months ago
    A New Full Adder Cell for Low-Power Applications
    Download  140.128.95.1
    Ahmed M. Shams, Magdy A. Bayoumi
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    GLVLSI
    1998
    IEEE
    129views VLSI» more  GLVLSI 1998»
    Tabu Search Based Circuit Optimization
    13 years 11 months ago
    Tabu Search Based Circuit Optimization
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    In this paper we address the problem of optimizing mixed CMOS BiCMOS circuits. The problem is formulated as a constrained combinatorial optimization problem and solved using an ta...
    Sadiq M. Sait, Habib Youssef, Munir M. Zahra
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    GLVLSI
    1998
    IEEE
    99views VLSI» more  GLVLSI 1998»
    A Self Timed Asynchronous Router for an Heterogeneous Parallel Machine
    13 years 11 months ago
    A Self Timed Asynchronous Router for an Heterogeneous Parallel Machine
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    Eric Senn, Bertrand Zavidovique
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    GLVLSI
    1998
    IEEE
    83views VLSI» more  GLVLSI 1998»
    A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits
    13 years 11 months ago
    A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits
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    Kaamran Raahemifar, Majid Ahmadi
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    GLVLSI
    1998
    IEEE
    106views VLSI» more  GLVLSI 1998»
    Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling
    13 years 11 months ago
    Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling
    Download  www.cs.york.ac.uk
    Irith Pomeranz, Sudhakar M. Reddy
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    GLVLSI
    1998
    IEEE
    118views VLSI» more  GLVLSI 1998»
    Design of Clock Distribution Networks in Presence of Process Variations
    13 years 11 months ago
    Design of Clock Distribution Networks in Presence of Process Variations
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    Mohamed Nekili, Yvon Savaria, Guy Bois
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    GLVLSI
    1998
    IEEE
    107views VLSI» more  GLVLSI 1998»
    MDG-based Verification by Retiming and Combinational Transformations
    13 years 11 months ago
    MDG-based Verification by Retiming and Combinational Transformations
    Download  www.cs.york.ac.uk
    Otmane Aït Mohamed, Eduard Cerny, Xiaoyu Song
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    GLVLSI
    1998
    IEEE
    109views VLSI» more  GLVLSI 1998»
    A Quantitative Study of the Benefits of Area-I/O in FPGAs
    13 years 11 months ago
    A Quantitative Study of the Benefits of Area-I/O in FPGAs
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    Herwig Van Marck, Jo Depreitere, Dirk Stroobandt, ...
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    GLVLSI
    1998
    IEEE
    135views VLSI» more  GLVLSI 1998»
    The Chinese Abacus Method: Can We Use It for Digital Arithmetic?
    13 years 11 months ago
    The Chinese Abacus Method: Can We Use It for Digital Arithmetic?
    Download  www.cs.york.ac.uk
    Franco Maloberti, Chen Gang
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