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    CSREAESA
    2006
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    Delay-Reduced Combinational Logic Synthesis using Multiplexers
    14 years 28 days ago
    Delay-Reduced Combinational Logic Synthesis using Multiplexers
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    - This paper presents an approach to obtain reduced hardware and/or delay for synthesizing logic functions using multiplexers. Replication of single control line multiplexer is use...
    Rekha K. James, T. K. Shahana, K. Poulose Jacob, S...
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