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30

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MICRO
1995
IEEE

81views Hardware» more MICRO 1995»

The M-Machine multicomputer

14 years 5 days ago

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Marco Fillo, Stephen W. Keckler, William J. Dally,...

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37

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MICRO
1995
IEEE

217views Hardware» more MICRO 1995»

Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation

14 years 5 days ago

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Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...

Jack W. Davidson, Sanjay Jinturkar

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22

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MICRO
1995
IEEE

102views Hardware» more MICRO 1995»

Zero-cycle loads: microarchitecture support for reducing load latency

14 years 5 days ago

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Untolerated load instruction latencies often have a signiﬁcant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...

Todd M. Austin, Gurindar S. Sohi

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25

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MICRO
1995
IEEE

85views Hardware» more MICRO 1995»

The predictability of branches in libraries

14 years 5 days ago

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Brad Calder, Dirk Grunwald, Amitabh Srivastava

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29

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MICRO
1995
IEEE

140views Hardware» more MICRO 1995»

A system level perspective on branch architecture performance

14 years 5 days ago

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Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...

Brad Calder, Dirk Grunwald, Joel S. Emer

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24

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MICRO
1995
IEEE

72views Hardware» more MICRO 1995»

Dynamic rescheduling: a technique for object code compatibility in VLIW architectures

14 years 5 days ago

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Lack of object code compatibility in VLIW architectures is a severe limit to their adoption as a generalpurpose computing paradigm. Previous approaches include hardware and softwa...

Thomas M. Conte, Sumedh W. Sathaye

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15

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IWMM
1995
Springer

104views Hardware» more IWMM 1995»

Dynamic Storage Allocation: A Survey and Critical Review

14 years 5 days ago

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Paul R. Wilson, Mark S. Johnstone, Michael Neely, ...

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