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ICCAD
1991
IEEE
135views Hardware» more  ICCAD 1991»
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DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational Circuits
This paper presents an efficient algorithm for the generation of diagnostic test patterns which distinguish between two arbitrary single stuck-at faults. The algorithm is able to ...
Torsten Grüning, Udo Mahlstedt, Hartmut Koopm...
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
14 years 4 days ago
Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
Randal E. Bryant
ICCAD
1991
IEEE
76views Hardware» more  ICCAD 1991»
14 years 4 days ago
Flexible Block-Multiplier Generation
In a high level synthesis environment there is a strong need for flexible module generators. For the generation of regular structures efficient dedicated module generators can be ...
H. M. A. M. Arts, Jos T. J. van Eijndhoven, Leon S...
FACS
1991
170views Hardware» more  FACS 1991»
14 years 4 days ago
Deriving Measures of Software Reuse in Object Oriented Systems
The analysis and measurement of current levels of software reuse are necessary to monitor improvements. This paper provides a framework for the derivation of measures of software ...
James M. Bieman
CAV
1994
Springer
102views Hardware» more  CAV 1994»
14 years 4 days ago
The Mobility Workbench - A Tool for the pi-Calculus
Björn Victor, Faron Moller
VTS
1995
IEEE
100views Hardware» more  VTS 1995»
14 years 4 days ago
Transformed pseudo-random patterns for BIST
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
Nur A. Touba, Edward J. McCluskey
VTS
1995
IEEE
99views Hardware» more  VTS 1995»
14 years 4 days ago
Arithmetic built-in self test for high-level synthesis
In this paper, we propose an entirely new Built-In Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to...
Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerz...
VTS
1995
IEEE
94views Hardware» more  VTS 1995»
14 years 4 days ago
Synthesis of locally exhaustive test pattern generators
Optimized locally exhaustive test pattern generators based on linear sums promise a low overhead, but have an irregular structure. The paper presents a new algorithm able to compu...
Günter Kemnitz
VTS
1995
IEEE
105views Hardware» more  VTS 1995»
14 years 4 days ago
Cyclic stress tests for full scan circuits
To ensure the production of reliable circuits and fully testable unpackaged dies for MCMs burn-in, both dynamic and monitored, remains a feasible option. During this burn-in proce...
Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Jan...