Sciweavers

ISCA
2012
IEEE
281views Hardware» more  ISCA 2012»
11 years 9 months ago
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems
Memory system reliability is a serious and growing concern in modern servers. Existing chipkill-level memory protection mechanisms suffer from several drawbacks. They activate a l...
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev B...
ISCA
2012
IEEE
262views Hardware» more  ISCA 2012»
11 years 9 months ago
Boosting mobile GPU performance with a decoupled access/execute fragment processor
Smartphones represent one of the fastest growing markets, providing significant hardware/software improvements every few months. However, supporting these capabilities reduces the...
Jose-Maria Arnau, Joan-Manuel Parcerisa, Polychron...
ISCA
2012
IEEE
333views Hardware» more  ISCA 2012»
11 years 9 months ago
Reducing memory reference energy with opportunistic virtual caching
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
Arkaprava Basu, Mark D. Hill, Michael M. Swift
ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
11 years 9 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
ISCA
2012
IEEE
260views Hardware» more  ISCA 2012»
11 years 9 months ago
A case for exploiting subarray-level parallelism (SALP) in DRAM
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the h...
Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Li...
ISCA
2012
IEEE
224views Hardware» more  ISCA 2012»
11 years 9 months ago
A first-order mechanistic model for architectural vulnerability factor
Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probab...
Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy...
ISCA
2012
IEEE
218views Hardware» more  ISCA 2012»
11 years 9 months ago
Towards energy-proportional datacenter memory with mobile DRAM
To increase datacenter energy efficiency, we need memory systems that keep pace with processor efficiency gains. Currently, servers use DDR3 memory, which is designed for high b...
Krishna T. Malladi, Frank A. Nothaft, Karthika Per...
ISCA
2012
IEEE
261views Hardware» more  ISCA 2012»
11 years 9 months ago
RAIDR: Retention-aware intelligent DRAM refresh
Dynamic random-access memory (DRAM) is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh operation...
Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu
ISCA
2012
IEEE
191views Hardware» more  ISCA 2012»
11 years 9 months ago
VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors
Power consumption is a primary concern for microprocessor designers. Lowering the supply voltage of processors is one of the most effective techniques for improving their energy e...
Timothy N. Miller, Renji Thomas, Xiang Pan, Radu T...
ISCA
2012
IEEE
274views Hardware» more  ISCA 2012»
11 years 9 months ago
The dynamic granularity memory system
Chip multiprocessors enable continued performance scaling with increasingly many cores per chip. As the throughput of computation outpaces available memory bandwidth, however, the...
Doe Hyun Yoon, Min Kyu Jeong, Michael Sullivan, Ma...