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ISCA
1999
IEEE
87views Hardware» more  ISCA 1999»
14 years 1 months ago
Memory Forwarding: Enabling Aggressive Layout Optimizations by Guaranteeing the Safety of Data Relocation
By optimizing data layout at run-time, we can potentially enhance the performance of caches by actively creating spatial locality, facilitating prefetching, and avoiding cache con...
Chi-Keung Luk, Todd C. Mowry
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
14 years 1 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
ISCA
1999
IEEE
96views Hardware» more  ISCA 1999»
14 years 1 months ago
PipeRench: A Coprocessor for Streaming multimedia Acceleration
Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes ...
Seth Copen Goldstein, Herman Schmit, Matthew Moe, ...
ISCA
1999
IEEE
104views Hardware» more  ISCA 1999»
14 years 1 months ago
Is SC + ILP=RC?
Sequential consistency (SC) is the simplest programming interface for shared-memory systems but imposes program order among all memory operations, possibly precluding high perform...
Chris Gniady, Babak Falsafi, T. N. Vijaykumar
ISCA
1999
IEEE
89views Hardware» more  ISCA 1999»
14 years 1 months ago
Simultaneous Subordinate Microthreading (SSMT)
Current work in Simultaneous Multithreading provides little benefit to programs that aren't partitioned into threads. We propose Simultaneous Subordinate Microthreading (SSMT...
Robert S. Chappell, Jared Stark, Sangwook P. Kim, ...
ISCA
1999
IEEE
90views Hardware» more  ISCA 1999»
14 years 1 months ago
Selective Value Prediction
Value Prediction is a relatively new technique to increase instruction-level parallelism by breaking true data dependence chains. A value prediction architecture produces values, ...
Brad Calder, Glenn Reinman, Dean M. Tullsen
ISCA
1999
IEEE
94views Hardware» more  ISCA 1999»
14 years 1 months ago
A Performance Comparison of Contemporary DRAM Architectures
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor ...
ISCA
1999
IEEE
110views Hardware» more  ISCA 1999»
14 years 1 months ago
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
ISCA
1999
IEEE
124views Hardware» more  ISCA 1999»
14 years 1 months ago
The Block-Based Trace Cache
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
Bryan Black, Bohuslav Rychlik, John Paul Shen