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MICRO
2010
IEEE
189views Hardware» more  MICRO 2010»
13 years 4 months ago
A Dynamically Adaptable Hardware Transactional Memory
Most Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...
MICRO
2010
IEEE
210views Hardware» more  MICRO 2010»
13 years 4 months ago
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention...
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor H...
MICRO
2010
IEEE
121views Hardware» more  MICRO 2010»
13 years 4 months ago
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
Abstract--Emerging many-core chip multiprocessors will integrate dozens of small processing cores with an on-chip interconnect consisting of point-to-point links. The interconnect ...
Michael M. Lee, John Kim, Dennis Abts, Michael R. ...
MICRO
2010
IEEE
238views Hardware» more  MICRO 2010»
13 years 4 months ago
Sampling Dead Block Prediction for Last-Level Caches
Last-level caches (LLCs) are large structures with significant power requirements. They can be quite inefficient. On average, a cache block in a 2MB LRU-managed LLC is dead 86% of ...
Samira Manabi Khan, Yingying Tian, Daniel A. Jimen...
MICRO
2010
IEEE
142views Hardware» more  MICRO 2010»
13 years 4 months ago
Virtual Snooping: Filtering Snoops in Virtualized Multi-cores
Virtualization has been rapidly expanding its applications in numerous server and desktop environments to improve the utilization and manageability of physical systems. Such prolif...
Daehoon Kim, Hwanju Kim, Jaehyuk Huh
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 4 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
13 years 4 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...
MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
13 years 4 months ago
Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories
Emerging non-volatile memory technologies such as phase change memory (PCM) promise to increase storage system performance by a wide margin relative to both conventional disks and ...
Adrian M. Caulfield, Arup De, Joel Coburn, Todor I...
MICRO
2010
IEEE
159views Hardware» more  MICRO 2010»
13 years 4 months ago
Fractal Coherence: Scalably Verifiable Cache Coherence
We propose an architectural design methodology for designing formally verifiable cache coherence protocols, called Fractal Coherence. Properly designed to be fractal in behavior, t...
Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin
MICRO
2010
IEEE
145views Hardware» more  MICRO 2010»
13 years 4 months ago
Combating Aging with the Colt Duty Cycle Equalizer
Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause severe lifetime degradation in the performance and the reliability of future CMOS devices. Th...
Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mi...