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    ASPLOS
    2006
    ACM
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    Instruction scheduling for a tiled dataflow architecture
    14 years 3 months ago
    Instruction scheduling for a tiled dataflow architecture
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    This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effective...
    Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
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