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    ICCD
    2002
    IEEE
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    Balancing the Interconnect Topology for Arrays of Processors between Cost and Power
    14 years 8 months ago
    Balancing the Interconnect Topology for Arrays of Processors between Cost and Power
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    High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
    Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Che...
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