HIPEAC
2009
Springer
14 years 3 months ago
2009
Springer
Shrinking process technologies and growing chip sizes have profound effects on process variation. This leads to Chip Multiprocessors (CMPs) where not all cores operate at maximum f...
HIPEAC
2009
Springer
14 years 4 months ago
2009
Springer
Abstract. On multi-core architectures with software-managed memories, effectively orchestrating data movement is essential to performance, but is tedious and error-prone. In this p...
HIPEAC
2009
Springer
14 years 4 months ago
2009
Springer
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
HIPEAC
2009
Springer
14 years 4 months ago
2009
Springer
Abstract. This paper advocates the placement of Architecturally Visible Communication (AVC) buffers between adjacent cores in MPSoCs to provide highthroughput communication for str...
HIPEAC
2009
Springer
14 years 4 months ago
2009
Springer
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient sh...
HIPEAC
2009
Springer
14 years 5 months ago
2009
Springer
Abstract. In transactional memory, aborted transactions reduce performance, and waste computing resources. Ideally, concurrent execution of transactions should be optimally ordered...
HIPEAC
2009
Springer
14 years 5 months ago
2009
Springer
Abstract. Technological advances and increasingly complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application charac...
HIPEAC
2009
Springer
14 years 7 months ago
2009
Springer
In previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is based on the observation that inte...
HIPEAC
2009
Springer
14 years 7 months ago
2009
Springer
Abstract. Threads experiencing long-latency loads on a simultaneous multithreading (SMT) processor may clog shared processor resources without making forward progress, thereby star...
HIPEAC
2009
Springer
14 years 7 months ago
2009
Springer
Abstract. Iterative compilation is an efficient approach to optimize programs on rapidly evolving hardware, but it is still only scarcely used in practice due to a necessity to gat...