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ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
David Blaauw, Vladimir Zolotov, Savithri Sundaresw...
Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a s...
Synchronous Data Flow (SDF) is a well-known model of computation that is widely used in the control engineering and digital signal processing domains. Existing scheduling methods ...
In this paper, we propose a novel misted-bundle layout structure for minimizing inductive coupling noise. In this structure,we create severalrouting regions and re-order the routi...
In this paper, we propose an approach for the analysis of power supply noise in the frequency domain for power/ground (P/G) networks of tree topologies. We model the P/G network a...
We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and...
In this paper, we develop a new standard cell placement tool, Dragon2000, to solve large scale placement problem effectively. A top-down hierarchical approach is used in Dragon200...
This paper presents an efficient method for optimizing power/ground (P/G) networks by widening wires and adding decoupling capacitors (decaps). It proposes a structured skeleton t...