Sciweavers

ICCD
2000
IEEE
107views Hardware» more  ICCD 2000»
14 years 4 months ago
Architectural Impact of Secure Socket Layer on Internet Servers
Secure socket layer SSL is the most popular protocol used in the Internet for facilitating secure communications through authentication, encryption, and decryption. Although the...
Krishna Kant, Ravishankar K. Iyer, Prasant Mohapat...
ICCD
2000
IEEE
87views Hardware» more  ICCD 2000»
14 years 4 months ago
A Register File with Transposed Access Mode
We introduce a new register file architecture that provides both row-wise and column-wise accesses, thus allowing partitioned instructions to be used in columnwise processing with...
Yoochang Jung, Stefan G. Berg, Donglok Kim, Yongmi...
ICCD
2000
IEEE
88views Hardware» more  ICCD 2000»
14 years 4 months ago
Efficient Design Error Correction of Digital Circuits
Dirk W. Hoffmann, Thomas Kropf
ICCD
2000
IEEE
123views Hardware» more  ICCD 2000»
14 years 4 months ago
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits
This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating of the ground bounce is presen...
Payam Heydari, Massoud Pedram
ICCD
2000
IEEE
116views Hardware» more  ICCD 2000»
14 years 4 months ago
Representing and Scheduling Looping Behavior Symbolically
This paper presents a very general, exact technique for scheduling looping data-flow graphs. In contrast to the conventional technique using loop iteration variables and integer ...
Steve Haynal, Forrest Brewer
ICCD
2000
IEEE
93views Hardware» more  ICCD 2000»
14 years 4 months ago
Cheap Out-of-Order Execution Using Delayed Issue
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
J. P. Grossman
ICCD
2000
IEEE
135views Hardware» more  ICCD 2000»
14 years 4 months ago
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration
el of abstraction by integrating a high-level estimation step. This results in a design loop which is tight led on high level of abstraction (called estimation loop in figure 1). ...
Joachim Gerlach, Wolfgang Rosenstiel
ICCD
2000
IEEE
125views Hardware» more  ICCD 2000»
14 years 4 months ago
Architectural Support for Dynamic Memory Management
Recent advances in software engineering, such as graphical user intevaces and object-oriented programming, have caused applications to become more memory intensive. These applicat...
J. Morris Chang, Witawas Srisa-an, Chia-Tien Dan L...
ICCD
2000
IEEE
103views Hardware» more  ICCD 2000»
14 years 4 months ago
Efficient Place and Route for Pipeline Reconfigurable Architectures
In this paper, we present a fast and eficient compilation methodology for pipeline reconfigurable architectures. Our compiler back-end is much faster than conventional CAD tools, ...
Srihari Cadambi, Seth Copen Goldstein
ICCD
2000
IEEE
75views Hardware» more  ICCD 2000»
14 years 4 months ago
Hybridizing and Coalescing Load Value Predictors
Most well-performing load value predictors are hybrids that combine multiple predictors into one. Such hybrids are often large. To reduce their size and to improve their performan...
Martin Burtscher, Benjamin G. Zorn