This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches. The idea is based on a tight...
In system-on-a-chip design, interfacing of Intellectual Property(IP) blocks is one of the most important issues. Since most IP’s are provided by different vendors, they have dif...
Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min ...
AMULET3 is a 32-bit asynchronous processor core that is fully instruction set compatible with the clocked ARM cores. It represents the culmination of ten years of research and dev...
Stephen B. Furber, David A. Edwards, Jim D. Garsid...
An improved design of a dynamic Flip-Flop is presented. Proposed design overcomes the problem of the glitch at the output and improves Power-Delay Product for about 10%, while pre...
We present a local clocking mechanism based on a tunable delay line which calibrates itself from a low frequency global clock. After initial tuning, the local clock remains calibr...
Simon W. Moore, George S. Taylor, Paul A. Cunningh...
This research proposes a new cache system that can increase the effect by temporal and spatial locality by using only simple hardware control without any locality detection hardwa...
This paper presents a new method to extract functionally equivalent structures from logic netlists. It uses a fast functional regularity extraction algorithm based on structural e...
: Mobile processors form a large and very fast growing segment of semiconductor market. Although they are used in a great variety of embedded systems such as personal digital organ...