ISCA
1994
IEEE
14 years 4 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
ISCA
1994
IEEE
14 years 4 months ago
1994
IEEE
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
ISCA
1994
IEEE
14 years 4 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
ISCA
1994
IEEE
14 years 4 months ago
1994
IEEE
ISCA
1994
IEEE
14 years 4 months ago
1994
IEEE
This paper presents an examination of different cache and processor configurations assuming transistor densities will continue to increase as they have in the past. While in the s...
ISCA
1994
IEEE
14 years 4 months ago
1994
IEEE
ISCA
1994
IEEE
14 years 4 months ago
1994
IEEE
In 1989, the RAID (Redundant Arrays of Inexpensive Disks) group at U. C. Berkeley built a prototype disk array called RAID-I. The bandwidth delivered to clients by RAID-I was seve...
ISCA
1994
IEEE
14 years 4 months ago
1994
IEEE
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...
ISCA
1994
IEEE
14 years 4 months ago
1994
IEEE
Wepresentaunijiedapp?'each to assess thet7adeoff of architecture techniques that affect mean memory access time. The architectural features we consider inciude cache hit Tati...
ISCA
1994
IEEE
14 years 4 months ago
1994
IEEE