ISCAS
2003
IEEE
14 years 5 months ago
2003
IEEE
ISCAS
2003
IEEE
14 years 5 months ago
2003
IEEE
In this paper, we introduce a tile-graph-based approach to power planning. For a given flooplan solution, the power inputs are modeled into a tile graph, the minimum capacity of e...
ISCAS
2003
IEEE
14 years 5 months ago
2003
IEEE
— The authors present a number of complete cores which are specially tailored for the low power implementation of FIR filters executed using block processing. The paper reveals t...
ISCAS
2003
IEEE
14 years 5 months ago
2003
IEEE
ISCAS
2003
IEEE
14 years 5 months ago
2003
IEEE
ISCAS
2003
IEEE
14 years 5 months ago
2003
IEEE
The width of an interconnect line a ects the total power consumed by a circuit. A tradeo exists, however, between the dynamic power and the short-circuit power in determining the ...
ISCAS
2003
IEEE
14 years 5 months ago
2003
IEEE
Ordered Binary Decision Diagrams (BDDs) are frequently used in logic synthesis. In this paper a new exact BDD minimization algorithm is presented, which is based on state space se...
ISCAS
2003
IEEE
14 years 5 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
ISCAS
2003
IEEE
14 years 5 months ago
2003
IEEE
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
ISCAS
2003
IEEE
14 years 5 months ago
2003
IEEE
