—A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (...
Abstract— Robust H.264/SVC video multicast with joint network coding (NC) and application-layer forward error correction (AL-FEC) is presented in this work. Unlike traditional AL...
—Chemiresistive (CR) sensors and sensor arrays coated with thiolate-monolayer-protected gold nanoparticle (MPN) interfaces show great promise for high-sensitivity multi-vapor ana...
Daniel Rairigh, Andrew Mason, Michael P. Rowe, Edw...
— A fully differential translinear 3-phase sinusoidal oscillator architecture is presented. The architecture is meant for BiCMOS implementation and uses only NPN devices, typical...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...
—An energy detector designed in a 0.18μm CMOS technology and intended for a non-coherent impulse-radio UWB receiver is presented in this paper. The proposed circuit exploits the...
Andrea Gerosa, Maurizio Dalla Costa, Andrea Bevila...
— Recently four chaos-based image encryption schemes were proposed. Essentially, the four schemes can be classified into one class, which is composed of two basic parts: permuta...
— In this paper, a new hybrid photodiode-photogate (HPDPG) CMOS APS pixel for high-dynamic range imaging applications is presented. The HPDPG pixel composes of a biased photogate...