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ISMVL
2009
IEEE
88views Hardware» more  ISMVL 2009»
14 years 6 months ago
Minimal Coverings of Maximal Partial Clones
A partial function f on an k-element set Ek is a partial Sheffer function if every partial function on Ek is definable in terms of f. Since this holds if and only if f belongs to...
Karsten Schölzel
ISMVL
2009
IEEE
161views Hardware» more  ISMVL 2009»
14 years 6 months ago
Mining Approximative Descriptions of Sets Using Rough Sets
Using concepts from rough set theory we investigate the existence of approximative descriptions of collections of objects that can be extracted from data sets, a problem of intere...
Dan A. Simovici, Selim Mimaroglu
ISMVL
2009
IEEE
189views Hardware» more  ISMVL 2009»
14 years 6 months ago
A Quaternary Decision Diagram Machine and the Optimization of its Code
We show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which y...
Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura,...
ISMVL
2009
IEEE
124views Hardware» more  ISMVL 2009»
14 years 6 months ago
Equivalence Checking of Reversible Circuits
Determining the equivalence of reversible circuits designed to meet a common specification is considered. The circuits’ primary inputs and outputs must be in pure logic states ...
Robert Wille, Daniel Große, D. Michael Mille...
ISMVL
2009
IEEE
94views Hardware» more  ISMVL 2009»
14 years 6 months ago
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions
This paper proposes a design method for floating-point numerical function generators (NFGs) using multi-valued decision diagrams (MDDs). Our method applies to monotone elementary...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
ISMVL
2009
IEEE
78views Hardware» more  ISMVL 2009»
14 years 6 months ago
Frozen Boolean Partial Co-clones
We introduce and investigate the concept of frozen partial co-clones. Our main motivation for studying frozen partial co-clones is that they have important applications in complex...
Gustav Nordh, Bruno Zanuttini
ISMVL
2009
IEEE
94views Hardware» more  ISMVL 2009»
14 years 6 months ago
Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©
Satyendra R. Datla, Mitchell A. Thornton, Luther H...
ISMVL
2009
IEEE
96views Hardware» more  ISMVL 2009»
14 years 6 months ago
Evaluation of Cardinality Constraints on SMT-Based Debugging
For formal verification of hardware Satisfiability Modulo Theory (SMT) solvers are increasingly applied. Today’s state-of-the-art SMT solvers use different techniques like ter...
André Sülflow, Robert Wille, Görs...
ISMVL
2009
IEEE
107views Hardware» more  ISMVL 2009»
14 years 6 months ago
Regular Encodings from Max-CSP into Partial Max-SAT
We define a number of original encodings, called regular encodings, that map Max-CSP instances into Partial MaxSAT instances. First, we obtain new direct and (minimal) support en...
Josep Argelich, Alba Cabiscol, Inês Lynce, F...