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25

ISMVL
2009
IEEE

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Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©

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Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©

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Satyendra R. Datla, Mitchell A. Thornton, Luther H

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Artificial Intelligence | ISMVL 2009 |

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Added	24 May 2010
Updated	24 May 2010
Type	Conference
Year	2009
Where	ISMVL
Authors	Satyendra R. Datla, Mitchell A. Thornton, Luther Hendrix, Dave Henderson

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