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ISMVL
2010
IEEE
140views Hardware» more  ISMVL 2010»
13 years 9 months ago
Efficient Simulation-Based Debugging of Reversible Logic
Stefan Frehse, Robert Wille, Rolf Drechsler
ISMVL
2010
IEEE
161views Hardware» more  ISMVL 2010»
14 years 24 days ago
Revisiting Ultraproducts in Fuzzy Predicate Logics
—In this paper we examine different possibilities of defining reduced products and ultraproducts in fuzzy predicate logics. We present analogues to the Łos Theorem for these no...
Pilar Dellunde
ISMVL
2010
IEEE
166views Hardware» more  ISMVL 2010»
14 years 2 months ago
Non-deterministic Multi-valued Logics--A Tutorial
Non-deterministic multi-valued matrices (Nmatrices) are a new, fruitful and quickly expanding field of research first introduced a few years ago. Since then it has been rapidly ...
Arnon Avron, Anna Zamansky
ISMVL
2010
IEEE
158views Hardware» more  ISMVL 2010»
14 years 2 months ago
An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions
—Using EXOR gates in logic synthesis often results in smaller circuit realizations. While in AND/OR synthesis the problem definition is clear, in AND/EXOR synthesis several clas...
Alexander Finder, Rolf Drechsler
ISMVL
2010
IEEE
186views Hardware» more  ISMVL 2010»
14 years 3 months ago
A Classification of Partial Boolean Clones
We study intervals I(A) of partial clones whose total functions constitute a (total) clone A. In the Boolean case, we provide a complete classification of such intervals (accordin...
Dietlinde Lau, Karsten Schölzel
ISMVL
2010
IEEE
174views Hardware» more  ISMVL 2010»
14 years 3 months ago
Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits
—Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is bas...
Satyendra R. Datla, Mitchell A. Thornton
ISMVL
2010
IEEE
156views Hardware» more  ISMVL 2010»
14 years 3 months ago
Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs
This paper proposes a new architecture for memorybased floating-point numeric function generators (NFGs). The design method uses piecewise-split edge-valued multivalued decision ...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
ISMVL
2010
IEEE
191views Hardware» more  ISMVL 2010»
14 years 3 months ago
Toffoli Gate Implementation Using the Billiard Ball Model
— In this paper we review the Billiard Ball Model (BBM) introduced by Toffoli and Fredkin. The analysis of a previous approach to design reversible networks based on BBM it shown...
Hadi Hosseini, Gerhard W. Dueck
ISMVL
2010
IEEE
195views Hardware» more  ISMVL 2010»
14 years 3 months ago
ESOP-Based Toffoli Network Generation with Transformations
In this paper a new Toffoli gate cascade synthesis method is presented. This method is based on previous work [12] and generates a cascade of inverted-control-Toffoli gates from t...
Yasaman Sanaee, Gerhard W. Dueck