modules can be handled in constraint graphs efficiently. This Floorplan area minimization is an important problem because many modules have shape flexibilities during the floorplan...
Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. W...
The standard cell placement problem has been extensively studied in the past twenty years. Many approaches were proposed and proven e ective in practice. However, successful place...
As technology advances, more and more issues need to be considered in the placement stage, e.g., wirelength, congestion, timing, coupling. It is very hard to consider all of them ...
In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...
We address the problem of computing critical area for missing material defects in a circuit layout. The extraction of critical area is the main computational problem in VLSI yield...
Recently, a deterministic algorithm based on the O-tree representation has been proposed. This method generates excellent layout results on MCNC test cases with O(n3 ) complexity,...
In this paper we present a repeater block planning algorithm for interconnect-centric floorplanning. We introduce the concept of independent feasible regions for repeaters and der...