This paper presents a fast algorithm to optimize both the widths and lengths of power/ground networks under reliability and power dip/ground bounce constraints. The spacesizing wh...
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Diagrams (BDDs) and SAT...
The reliability of ADCs used in highly critical systems can be increased by applying a two-step procedure starting with sensitivity analysis followed by redesign. The sensitivity ...
All synchronous CMOS integrated systems have to pay some sequencing overhead. This overhead includes the skew and the jitter of the clock. It also includes the setup time and the ...
Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S...
— The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evalua...
This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew....
Enrico Malavasi, Stefano Zanella, Min Cao, Julian ...
Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consu...
The design methods and the automation of the comparator circuit layout generation for a flash A/D converter are presented in this paper. The threshold inverter quantization (TIQ)...
With advancing semiconductor technology and exponentially growing design complexities, predictability of design tools becomes an important part of a stable top-down design process...