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    DAC
    2008
    ACM
    145views Computer Architecture» more  DAC 2008»
    Enhancing timing-driven FPGA placement for pipelined netlists
    15 years 14 days ago
    Enhancing timing-driven FPGA placement for pipelined netlists
    Download  www.ee.washington.edu
    FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
    Kenneth Eguro, Scott Hauck
    claim paper
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