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32
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ISQED
2006
IEEE
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ISQED 2006
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Impact of Gate-Length Biasing on Threshold-Voltage Selection
14 years 5 months ago
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vlsicad.ucsd.edu
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly ...
Andrew B. Kahng, Swamy Muddu, Puneet Sharma
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