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    GLVLSI
    2009
    IEEE
    164views VLSI» more  GLVLSI 2009»
    Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
    14 years 6 months ago
    Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
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    In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power im...
    Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Da...
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