Sciweavers

CDES
2006
98views Hardware» more  CDES 2006»
14 years 26 days ago
Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer
Recently, several loop buffer designs have been proposed to reduce instruction fetch energy due to size and location advantage of loop buffer. Nevertheless, on design complexity di...
Bin-Hua Tein, I-Wei Wu, Chung-Ping Chung
LCTRTS
1999
Springer
14 years 3 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...
ASPDAC
2004
ACM
129views Hardware» more  ASPDAC 2004»
14 years 4 months ago
Instruction buffering exploration for low energy VLIWs with instruction clusters
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
Tom Vander Aa, Murali Jayapala, Francisco Barat, G...