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TVLSI
2010
13 years 6 months ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas
ISCAS
2008
IEEE
109views Hardware» more  ISCAS 2008»
14 years 6 months ago
A low-area interconnect architecture for chip multiprocessors
— A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, th...
Zhiyi Yu, Bevan M. Baas