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    DATE
    2006
    IEEE
    119views Hardware» more  DATE 2006»
    Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
    14 years 5 months ago
    Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
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    The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
    Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
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