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    ASPDAC
    2009
    ACM
    127views Hardware» more  ASPDAC 2009»
    Timing driven power gating in high-level synthesis
    14 years 9 months ago
    Timing driven power gating in high-level synthesis
    Download  rd.cycu.edu.tw
    - The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock ...
    Shih-Hsu Huang, Chun-Hua Cheng
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