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HPCA
2011
IEEE
12 years 10 months ago
A new server I/O architecture for high speed networks
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
Guangdeng Liao, Xia Znu, Laxmi N. Bhuyan
MICRO
1999
IEEE
143views Hardware» more  MICRO 1999»
13 years 11 months ago
Code Transformations to Improve Memory Parallelism
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
Vijay S. Pai, Sarita V. Adve