Sciweavers

ICCAD
2008
IEEE
147views Hardware» more  ICCAD 2008»
14 years 9 months ago
Overlay aware interconnect and timing variation modeling for double patterning technology
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
Jae-Seok Yang, David Z. Pan