MICRO 1991 | Sciweavers

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MICRO
1991
IEEE

94views Hardware» more MICRO 1991»

Two-Level Adaptive Training Branch Prediction

14 years 2 months ago

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Tse-Yu Yeh, Yale N. Patt

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MICRO
1991
IEEE

115views Hardware» more MICRO 1991»

Executing Loops on a Fine-Grained MIMD Architecture

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- We present techniques for exploiting parallelism extracted from loops on an MIMD system. Parallelism is exploited through parallel execution of instructions on multiple processor...

Sunah Lee, Rajiv Gupta

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MICRO
1991
IEEE

126views Hardware» more MICRO 1991»

Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching

14 years 2 months ago

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The performance of superscalar processors is more sensitive to the memory system delay than their single-issue predecessors. This paper examines alternative data access microarchi...

William Y. Chen, Scott A. Mahlke, Pohua P. Chang, ...

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MICRO
1991
IEEE

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Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors

14 years 2 months ago

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This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...

Pohua P. Chang, William Y. Chen, Scott A. Mahlke, ...

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MICRO
1991
IEEE

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Strategies for Branch Target Buffers

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Brian K. Bray, Michael J. Flynn

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