Sciweavers

IPPS
2003
IEEE
14 years 4 months ago
Miss Penalty Reduction Using Bundled Capacity Prefetching in Multiprocessors
While prefetch has proven itself useful for reducing cache misses in multiprocessors, traffic is often increased due to extra unused prefetch data. Prefetching in multiprocessors...
Dan Wallin, Erik Hagersten
ICPP
2003
IEEE
14 years 4 months ago
Towards Real-time Parallel Processing of Spatial Queries
Spatial databases are entering an era of mass deployment in various real-life applications, especially mobile and location-based services. The real-time processing of spatial quer...
Haibo Hu, Manli Zhu, Dik Lun Lee
LCPC
2004
Springer
14 years 4 months ago
Phase-Based Miss Rate Prediction Across Program Inputs
Previous work shows the possibility of predicting the cache miss rate (CMR) for all inputs of a program. However, most optimization techniques need to know more than the miss rate ...
Xipeng Shen, Yutao Zhong, Chen Ding
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
14 years 5 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang