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    VTS
    2003
    IEEE
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    Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs
    14 years 5 months ago
    Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs
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    Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimizati...
    Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Kr...
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