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    2008
    IEEE
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    A nano-CMOS process variation induced read failure tolerant SRAM cell
    14 years 5 months ago
    A nano-CMOS process variation induced read failure tolerant SRAM cell
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    — In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is...
    Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...
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