PDP
2010
IEEE
13 years 9 months ago
2010
IEEE
— This paper presents Investigation of Transient Fault Effects in an asynchronous NoC router. The experiment is based on simulation-based fault injection method to assess the fau...
ERSA
2006
14 years 25 days ago
2006
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
CODES
2007
IEEE
14 years 5 months ago
2007
IEEE
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...