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    FPGA
    1995
    ACM
    105views FPGA» more  FPGA 1995»
    On Nominal Delay Minimization in LUT-based FPGA Technology Mapping
    14 years 9 months ago
    On Nominal Delay Minimization in LUT-based FPGA Technology Mapping
    Download  cadlab.cs.ucla.edu
    We study the nominal delay minimization problem in LUTbased FPGA technologymapping, where interconnect delay is assumed proportionalto net fanout size. We prove that the delay-opt...
    Jason Cong, Yuzheng Ding
    claim paper
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