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FPGA
1995
ACM

On Nominal Delay Minimization in LUT-based FPGA Technology Mapping

14 years 3 months ago
On Nominal Delay Minimization in LUT-based FPGA Technology Mapping
We study the nominal delay minimization problem in LUTbased FPGA technologymapping, where interconnect delay is assumed proportionalto net fanout size. We prove that the delay-optimal K-LUT mapping problem under the nominal delay model is NP-hard when K  3, and remains NP-hard for duplication-free mapping and tree-based mapping for K  5 (but is polynomial time solvable for K = 2). We also present a simple heuristic to take nominal delay into consideration during LUT mapping for delay minimization.
Jason Cong, Yuzheng Ding
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where FPGA
Authors Jason Cong, Yuzheng Ding
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