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CDES
2009
87views Hardware» more  CDES 2009»
14 years 17 days ago
Delay-Insensitive Ternary Logic
This paper develops a delay-insensitive (DI) digital design paradigm that utilizes ternary logic as an alternative to dual-rail logic for encoding the DATA and NULL states. This ne...
Ravi Sankar Parameswaran Nair, Scott C. Smith, Jia...
ASYNC
2002
IEEE
114views Hardware» more  ASYNC 2002»
14 years 4 months ago
Checking Delay-Insensitivity: 104 Gates and Beyond
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...
Alex Kondratyev, Oriol Roig, Lawrence Neukom, Karl...