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ISCAS
2011
IEEE
288views Hardware» more  ISCAS 2011»
13 years 3 months ago
Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
Yang Sun, Guohui Wang, Joseph R. Cavallaro
TCOM
2008
151views more  TCOM 2008»
13 years 10 months ago
Design of regular (2, dc)-LDPC codes over GF(q) using their binary images
In this paper, a method to design regular (2, dc)-LDPC codes over GF(q) with both good waterfall and error floor properties is presented, based on the algebraic properties of thei...
Charly Poulliat, Marc P. C. Fossorier, David Decle...
GLOBECOM
2009
IEEE
14 years 2 months ago
Near-Shannon-Limit Linear-Time-Encodable Nonbinary Irregular LDPC Codes
—In this paper, we present a novel method to construct nonbinary irregular LDPC codes whose parity check matrix has only column weights of 2 and t, where t ≥ 3. The constructed...
Jie Huang, Shengli Zhou, Peter Willett
ICASSP
2008
IEEE
14 years 5 months ago
Structure of non-binary regular ldpc cycle codes
In this paper, we study non-binary regular LDPC cycle codes whose parity check matrix has fixed column weight 2 and fixed row weight d. We prove that the parity check matrix of ...
Jie Huang, Shengli Zhou, Peter Willett