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    ISPASS
    2006
    IEEE
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    Automatic testcase synthesis and performance model validation for high performance PowerPC processors
    14 years 5 months ago
    Automatic testcase synthesis and performance model validation for high performance PowerPC processors
    Download  lca.ece.utexas.edu
    The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
    Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John,...
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