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GLVLSI
2005
IEEE

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An FPGA design of AES encryption circuit with 128-bit keys

14 years 5 months ago

This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...

Hui Qin, Tsutomu Sasao, Yukihiro Iguchi

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