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    INTEGRATION
    2008
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    A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
    13 years 11 months ago
    A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
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    This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
    Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, And...
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