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    ISCAS
    2006
    IEEE
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    Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking
    14 years 6 months ago
    Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking
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    —A low-latency, HDL-synthesizable dynamic clock frequency controller is presented as a time-efficient alternative to full-custom implementations. Frequency division of a fully in...
    Robert M. Senger, Eric D. Marsman, Gordy A. Carich...
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