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33
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DAC
1999
ACM
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Computer Architecture
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DAC 1999
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A Two-State Methodology for RTL Logic Simulation
14 years 3 months ago
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www.cecs.uci.edu
This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Exampl...
Lionel Bening
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