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TCAD
2008
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TCAD 2008
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Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog
14 years 16 days ago
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el Predicate Abstraction and Refinement Techniques for Verifying RTL Verilog Himanshu Jain, Daniel Kroening, Natasha Sharygina, and Edmund M. Clarke, Fellow, IEEE As a first step, ...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...
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