In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
This paper presents a novel micro-architecture for high-performance and low-power DSPs. The underlying Synchronous Transfer Architecture (STA) fills the gap between SIMD-DSPs and ...
Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil...
Abstract. This article presents a novel design flow called MOUSE for the effective development of digital signal processing systems in terms of development time, performance and p...
Today’s Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which s...
Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Ra...
Abstract. Loop unrolling plays an important role in compilation for Reconfigurable Processing Units (RPUs) as it exposes operator parallelism and enables other transformations (e.g...
Abstract. This paper presents some interesting concepts of static dataflow machines that can be used by reconfigurable computing architectures. We introduce some data-driven reconf...
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
Abstract. The focus of this work is on techniques that promise to reduce the message delivery latency in message passing environments, incuding clusters of workstations or SMPs. We...
Embedded digital signal processors for baseband communication systems have stringent design constraints including high computational bandwidth, low power consumption, and low inter...
Michael J. Schulte, C. John Glossner, Suman Mamidi...